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Low Cost 4-Channel 1 MSPS 16-Bit ADC AD7655*
FEATURES 4-Channel, 16-Bit Resolution ADC 2 Track-and-Hold Amplifiers Throughput: 1 MSPS (Normal Mode) 888 kSPS (Impulse Mode) Analog Input Voltage Range: 0 V to 5 V No Pipeline Delay Parallel and Serial 5 V/3 V Interface SPI(R)/QSPITM/MICROWIRETM/DSP Compatible Single 5 V Supply Operation Power Dissipation 120 mW Typical, 2.6 mW @ 10 kSPS Package: 48-Lead Quad Flat Pack (LQFP) or 48-Lead Frame Chip Scale Pack (LFCSP) Pin-to-Pin Compatible with the AD7654 Low Cost APPLICATIONS 4-Channel Data Acquisition FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REFGND REFx DVDD DGND OVDD OGND MUX MUX MUX PARALLEL INTERFACE SWITCHED CAP DAC 16 SERIAL PORT SER/PAR EOC BUSY D[15:0] CS RD A/B TRACK/HOLD 2
INA1 INAN INA2 A0 INB1 INBN INB2 PD RESET
CLOCK AND CONTROL LOGIC
AD7655
IMPULSE CNVST
BYTESWAP
PulSAR Selection Type/kSPS Pseudo Differential True Bipolar 18-Bit Multichannel/ Simultaneous PRODUCT HIGHLIGHTS 100-250 500-570 800-1000
GENERAL DESCRIPTION
AD7651 AD7650/AD7652 AD7653 AD7660/AD7661 AD7664/AD7666 AD7667 AD7663 AD7678 AD7665 AD7676 AD7679 AD7654 AD7655 AD7671 AD7677 AD7674
The AD7655 is a low cost, 4-channel, 16-bit, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. It contains two low noise, wide bandwidth track-andhold amplifiers that allow simultaneous sampling, a high speed 1 MSPS 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. Each track-and-hold has a multiplexer in front to provide a 4-channel input ADC. The AD7655 features a very high sampling rate mode (Normal) and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. It is available in 48-lead LQFP or 48-lead LFCSP packages with operation specified from -40C to +85C.
True Differential AD7675
1. Multichannel ADC The AD7655 features 4-channel inputs with two sampleand-hold circuits that allow simultaneous sampling. 2. Fast Throughput The AD7655 is a very high speed (1 MSPS in normal mode and 888 kSPS in impulse mode), charge redistribution, 16-bit SAR ADC that avoids pipeline delay. 3. Single-Supply Operation The AD7655 operates from a single 5 V supply and dissipates only 120 mW typical, even lower when a reduced throughput is used with the reduced power mode (Impulse) and a powerdown mode. 4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic.
*Patent pending
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
to +85 C, V = AD7655-SPECIFICATIONS (-40 Cotherwise noted.)2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless
REF
Parameter RESOLUTION ANALOG INPUT Voltage Range Common-mode Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle (2 channels) Throughput Rate Complete Cycle (2 channels) Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise Full-Scale Error2 Full-Scale Error Drift2 Unipolar Zero Error2 Unipolar Zero Error Drift2 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion)
Conditions
Min 16
Typ
Max
Unit Bits
VINx - VINxN VINxN fIN = 100 kHz 1 MSPS Throughput
0 -0.1 55 45 See Analog Input Section
2 VREF +0.5
V dB mA
In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode
0 0 -6 15
2 1 2.25 888 +6 0.8 0.25 2 0.8 0.8 86 98 -96 86 30 -92 10 2 30 5 0.5 0.25
ms MSPS ms kSPS LSB1 Bits LSB % of FSR ppm/ C % of FSR ppm/ C LSB dB3 dB dB dB dB dB MHz ns ps ps rms ns V mA
TMIN to TMAX TMIN to TMAX AVDD = 5 V 5% fIN = 100 kHz fIN = 100 kHz fIN = 100 kHz fIN = 100 kHz fIN = 100 kHz, -60 dB Input fIN = 100 kHz
Channel-to-Channel Isolation -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay4 Aperture Delay Matching4 Aperture Jitter4 Transient Response REFERENCE External Reference Voltage Range External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH
Full-Scale Step 2.3 1 MSPS Throughput 2.5 180
250 AVDD/2
-0.3 +2.0 -1 -1
+0.8 OVDD + 0.3 +1 +1
V V mA mA
ISINK = 1.6 mA ISOURCE = -500 mA
Parallel or Serial 16-Bit Straight Binary Coding Conversion Results Available Immediately after Completed Conversion 0.4 OVDD - 0.2
V V
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AD7655
Parameter POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current6 AVDD DVDD OVDD Power Dissipation Conditions Min Typ Max Unit
4.75 4.75 2.25 1 MSPS Throughput
5 5
5.25 5.25 5.255
V V V mA mA mA mW mW mW C
1 MSPS Throughput6 20 kSPS Throughput7 888 kSPS Throughput7
8
15.5 8.5 100 120 2.6 114 -40
135 125 +85
TEMPERATURE RANGE Specified Performance
TMIN to TMAX
NOTES 1 LSB means least significant bit. With the 0 V to 5 V input range, one LSB is 76.294 mV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Sample tested during initial release. 5 The maximum should be the minimum of 5.25 V and DVDD + 0.3 V. 6 In Normal Mode. 7 In Impulse Mode. 8 Contact factory for extended temperature range. Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
(-40 C to +85 C, VREF = 2.5 V, AVDD = AVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Min 5 2/2.25 32 1.75/2 Typ Max Unit ns ms ns ms ns ns ms ns ns ns ms ns ms ns ns ms ns ns ns ns
Refer to Figures 8 and 9 Convert Pulsewidth Time Between Conversions (Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read after Convert Mode (Normal Mode/Impulse Mode) Aperture Delay End of Conversions to BUSY LOW Delay Conversion Time (Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth CNVST LOW to EOC HIGH Delay EOC HIGH for Channel A Conversion (Normal Mode/Impulse Mode) EOC LOW after Channel A Conversion EOC HIGH for Channel B Conversion Channel Selection Setup Time Channel Selection Hold Time Refer to Figures 10, 11, 12, 13, and 14 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time A/B LOW to Data Valid Delay
2 10 1.75/2 250 10 30 1/1.25 45 0.75 250 30 1.75/2 14 5 40 15 40
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AD7655 TIMING SPECIFICATIONS (CONTINUED)
Parameter Refer to Figures 15 and 16 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Read during Convert) (Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay* Internal SCLK Period* Internal SCLK HIGH* Internal SCLK LOW* SDOUT Valid Setup Time* SDOUT Valid Hold Time* SCLK Last Edge to SYNC Delay* CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert (Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay (Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay Refer to Figures 17 and 18 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW Symbol t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 t44 5 3 5 5 25 10 10 3 23 12 7 4 2 1 Min Typ Max 10 10 10 250/500 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns
40
10 10 10 See Table I 0.75/1 25
18
*In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice.
Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum (Normal) Busy High Width Maximum (Impulse)
Symbol t25 t26 t26 t27 t28 t29 t30 t31 t35 t35
0 0 3 25 40 12 7 4 2 1 3.25 3.5
0 1 17 50 70 22 21 18 4 3 4.25 4.5
1 0 17 100 140 50 49 18 30 30 6.25 6.5
1 1 17 200 280 100 99 18 80 80 10.75 11
Unit ns ns ns ns ns ns ns ns ms ms
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AD7655
ABSOLUTE MAXIMUM RATINGS 1
Analog Inputs INAx2, INBx2, REFx, INxN, REFGND AGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Inputs . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . . 700 mW Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . . 2.5 W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91C/W, JC = 30C/W. 4 Specification is for device in free air: 48-Lead LFCSP: JA = 26C/W.
1.6mA
IOL
TO OUTPUT PIN
1.4V
CL 60pF* IOH
500 A
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
2V 0.8V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
Figure 2. Voltage Reference Levels for Timing
ORDERING GUIDE
Model AD7655AST AD7655ASTRL AD7655ACP AD7655ACPRL EVAL-AD7655CB1 EVAL-CONTROL BRD22
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Chip Scale Pack (LFCSP) Chip Scale Pack (LFCSP) Evaluation Board Controller Board
Package Option ST-48 ST-48 CP-48 CP-48
NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7655 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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AD7655
PIN CONFIGURATION
REFGND AGND AGND REFB REFA INAN INBN INA1 INA2 INB2 INB1 REF
36 35 34 33 32
48 47 46 45 44 43 42 41 40 39 38 37
AGND
1 PIN 1 IDENTIFIER
DVDD CNVST PD RESET CS RD EOC BUSY D15 D14 D13 D12
AVDD 2 A0 3 BYTESWAP 4 A/B 5 DGND 6 IMPULSE 7 SER/PAR 8 D0 9 D1 10 D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12
AD7655
TOP VIEW (Not to Scale)
31 30 29 28 27 26 25
13 14 15 16 17 18 19 20 21 22 23 24
OGND
DVDD
D4/EXT/INT D5/INVSYNC
DGND
PIN FUNCTION DESCRIPTIONS
Pin Number 1, 47, 48 2 3
Mnemonic AGND AVDD A0
Type P P DI
Description Analog Power Ground Pin. Input Analog Power Pin. Nominally 5 V. Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simultaneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled simultaneously, then converted. Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Data Channel Selection. In parallel mode, when LOW, the data from channel B is read. When HIGH, the data from channel A is read. In serial mode, when HIGH, channel A is output first followed by channel B. When LOW, channel B is output first followed by channel A. Digital Power Ground Pin. Mode Selection. When HIGH, this input selects a reduced power mode, IMPULSE. In this mode, the power dissipation is approximately proportional to the sampling rate. When LOW, the mode NORMAL is selected. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW which is the serial master read after convert mode, these inputs, part of the serial port, are used to slow down if desired the internal serial clock which clocks the data output. In the other serial modes, these inputs are not used. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called respectively, master and slave mode. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. -6- REV. 0
4 5
BYTESWAP A/B
DI DI
6, 20 7
DGND IMPULSE DI
8 9, 10 11, 12
SER/PAR D[0:1] D[2:3] or DIVSCLK[0:1]
DI DO DI/O
13
D[4] or EXT/INT
DI/O
14
D[5] or INVSYNC
DI/O
D11/RDERROR
D7/RDC/SDIN
D8/SDOUT
OVDD
D6/INVSCLK
D9/SCLK
D10/SYNC
AD7655
PIN FUNCTION DESCRIPTIONS
Pin Number 15
Mnemonic D[6] or INVSCLK
Type DI/O
Description When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH. When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as a incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the two conversions are complete and the data are latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. End of Convert Output. Going low at each channel conversion. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion if any is aborted. If not used, this pin could be tied to DGND.
16
D[7] DI/O or RDC/SDIN
17 18 19, 36 21
OGND OVDD DVDD D[8] or SDOUT
P P P DO
22
D[9] or SCLK
DI/O
23
D[10] or SYNC
DO
24
D[11] DO or RDERROR
25-28 29
D[12:15] BUSY
DO DO
30 31 32 33
EOC RD CS RESET
DO DI DI DI
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AD7655
PIN FUNCTION DESCRIPTIONS (continued)
Pin Number 34 35
Mnemonic PD CNVST
Type DI DI
Description Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH), if CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. This input pin is used to provide a reference to the converter. Reference Input Analog Ground Analog Inputs These inputs are the references applied to Channel A and Channel B, respectively. Analog input ground senses. Allow to sense each channel ground independently. Analog Inputs
37 38 39, 41 42, 43 40, 45 44, 46
REF REFGND INB1, INB2 REFB, REFA INBN, INAN INA2, INA1
AI AI AI AI AI AI
NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power
DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula:
ENOB = S / [ N + D ] dB - 1.76 / 6.02)
(
)
and is expressed in bits.
Total Harmonic Distortion (THD)
In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.
Full-Scale Error
THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.
Signal-to-Noise Ratio (SNR)
The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level.
Unipolar Zero Error
SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
In unipolar mode, the first transition should occur at a level 1/2 LSB above analog ground. The unipolar zero error is the deviation of the actual transition from that point.
Spurious Free Dynamic Range (SFDR)
S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels.
Aperture Delay
The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal.
Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signals are held for a conversion.
Transient Response
The time required for the AD7655 to achieve its rated accuracy after a full-scale step function is applied to its input.
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Typical Performance Characteristics-AD7655
5 4 3 2 DNL - LSB 32768 CODE INL - LSB 1 0 -1 -2 -3 -4 -5 0 16384 49152 65536 -3 0 16384 32768 CODE 49152 65536 2 1 3
0 -1
-2
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
8000 7059 6894 7000 6000
9000 8000 7000 6000
8480
5000
COUNTS
COUNTS
5000 4000 3000 2000 1000 739 0 0 102 5 103 220 104 105 106 107 CODE IN HEX 108 39 109 0 10A 3505 3396
4000 3000 2000 1094 1000 0 0 101 0 102 77 103 104 105 106 107 CODE IN HEX 29 108 0 109 0 10A 1230
TPC 2. Histogram of 16,384 Conversions of a DC Input at the Code Transition
TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Center
0 -20 8192 POINT FFT fS = 500MHz fIN = 100kHz, -0.5dB SNR = 85.8dB THD = -91.4dB SFDR = 93.6dB S/[N+D] = 84.5dB
96
-90
AMPLITUDE - dB of Full Scale
-40 -60 -80 -100 -120
93
-94
SNR - dB
90 THD
-98
87
-140 -160 -180 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY - kHz
R
-102
SNR
84 -55
-35
-15
5
25
45
65
85
105
-106 125
TEMPERATURE - C
TPC 3. FFT Plot
TPC 6. SNR, THD vs. Temperature
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THD - dB
AD7655
100 16.0 100 NORMAL AVDD 95
SNR AND S/[N+D] - dB
15.5 OPERATING CURRENTS - mA
10 NORMAL DVDD 1 IMPULSE AVDD 0.1 IMPULSE DVDD
90 SNR 85 SINAD 80 ENOB 75
15.0
ENOB - Bits
14.5
14.0
0.01
13.5
0.001
OVDD 2.7V
70 1 10 100 FREQUENCY - kHz
13.0 1000
0.0001 1 10 100 SAMPLING RATE - kSPS 1000
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
TPC 10. Operating Currents vs. Sample Rate
-75
50 OVDD = 2.7V @ 85 C
-80
THD, HARMONICS - dB
SFDR
OVDD = 2.7V @ 25 C 40
-85
t12 DELAY - ns
-90
CROSSTALK B TO A
30
-95 -100
CROSSTALK A TO B THD THIRD HARMONIC SECOND HARMONIC
OVDD = 5V @ 85 C 20 OVDD = 5V @ 25 C 10
-105
-110 1 10 100 FREQUENCY - kHz 1000
0
0
50
100 CL - pF
150
1000
TPC 8. THD, Harmonics, Crosstalk and SFDR vs. Frequency
TPC 11. Typical Delay vs. Load Capacitance CL
5 4 3 FULL SCALE 2 1 OFFSET DRIFT
LSB
0 -1 -2 -3 -4 -5 -55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE - C
TPC 9. Full Scale and Zero Error vs. Temperature
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AD7655
CIRCUIT INFORMATION
ADC CODE - Straight Binary
The AD7655 is a very fast, low power, single-supply, precise 4-channel 16-bit analog-to-digital converter (ADC). The AD7655 provides the user with two on-chip track-and-hold, successive approximation ADCs that do not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7655 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP or in a tiny 48-lead LFCSP package that combines space savings and allows flexible configurations as either serial or parallel interface. The AD7655 is pin-to-pin compatible with PulSAR ADCs.
Modes of Operation
111...111 111...110 111...101
000...010 000...001 000...000 -FS -FS + 1 LSB +FS - 1 LSB +FS - 1.5 LSB ANALOG INPUT
-FS + 0.5 LSB
The AD7655 features two modes of operation, normal and impulse. Each of these modes is more suitable for specific applications. The normal mode is the fastest mode (1 MSPS). Except when it is powered down (PD HIGH), the power dissipation is almost independent of the sampling rate. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 888 kSPS. When operating at 20 kSPS, for example, it typically consumes only 2.6 mW. This feature makes the AD7655 ideal for battery-powered applications.
Transfer Functions
Figure 3. ADC Ideal Transfer Function
Table II. Output Codes and Ideal Input Voltages
Description
FSR -1 LSB FSR - 2 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR
Analog Input VREF = 2.5 V 4.999924 V 4.999847 V 2.500076 V 2.5 V 2.499924 V -76.29 mV 0V
Digital Output Code (Hex) FFFF1 FFFE 8001 8000 7FFF 0001 00002
The AD7655 data format is straight binary. The ideal transfer characteristic for the AD7655 is shown in Figure 3 and Table II.
NOTES 1 This is also the code for overrange analog input (V INx - VINxN above 2 (VREF - VREFGND)). 2 This is also the code for underrange analog input (V INx below V INxN).
REV. 0
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AD7655
DVDD ANALOG SUPPLY (5V) 30 +
NOTE 6
DIGITAL SUPPLY (3.3V OR 5V) + 10 F 100nF 100nF + 10 F
10 F
100nF
AD780
2.5V REF
NOTE 1
AVDD 1M 100nF
NOTE 3
AGND
DGND
DVDD
OVDD
OGND SCLK SDOUT SERIAL PORT
50k
+ CREF
NOTE 2
1F
REF A/ REF B/ REF REFGND
50 - U1 + CC 15
BUSY CNVST 50 D
NOTE 7
C/ P/DSP
NOTE 4
INA1 2.7nF
NOTE 5
ANALOG INPUT A1
AD7655
SER/PAR DVDD
AD8021
50 - U2 + CC 15 2.7nF
NOTE 5
A/B A0 CS RD BYTESWAP RESET INAN PD CLOCK
NOTE 4
INA2
ANALOG INPUT A2
AD8021
50 - U1 + CC 15
NOTE 4
INB1 2.7nF
NOTE 5
ANALOG INPUT B1
AD8021
50 - U2 + CC 15 2.7nF
NOTE 4
INB2
ANALOG INPUT B2
AD8021
NOTE 5
INBN
NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. WITH THE RECOMMENDED VOLTAGE REFERENCES, CREF IS 47 F. SEE VOLTAGE REFERENCE INPUT SECTION. 3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 5. SEE ANALOG INPUTS SECTION. 6. OPTION, SEE POWER SUPPLY SECTION. 7. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.
Figure 4. Typical Connection Diagram (Serial Interface)
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AD7655
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7655. Different circuitry shown on this diagram is optional and is discussed below.
Analog Inputs
It could significantly differ from the settling time at a 16-bit level and, therefore, it should be verified prior to the driver selection. The tiny op amp AD8021, which combines ultralow noise and a high gain bandwidth, meets this settling time requirement even when used with a high gain of up to 13. The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7655. The noise coming from the driver is filtered by the AD7655 analog input circuit one-pole low-pass filter made by RA, RB, and CS. The driver needs to have a THD performance suitable to that of the AD7655.
Figure 5 shows a simplified analog input section of the AD7655.
AVDD
INA1 INA2 INAN INBN INB1 INB2
RA = 500 CS CS RB = 500
The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs an external compensation capacitor of 10 pF. This capacitor should have good linearity as an NPO ceramic or mica type. The AD8022 could also be used where a dual version is needed and a gain of 1 is used. The AD829 is another alternative where high frequency (above 100 kHz) performance is not required. In a gain of 1, it requires an 82 pF compensation capacitor. The AD8610 is also an option where low bias current is needed in low frequency applications.
Voltage Reference Input
AGND
Figure 5. Simplified Analog Input
The diodes shown in Figure 5 provide ESD protection for the inputs. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 120 mA maximum. This condition could eventually occur when the input buffer's (U1) or (U2) supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. This analog input structure allows the sampling of the differential signal between INx and INxN. Unlike other converters, the INxN is sampled at the same time as the INx input. By using these differential inputs, small signals common to both inputs are rejected. During the acquisition phase, for ac signals, the AD7655 behaves like a one-pole RC filter consisting of the equivalent resistance RA, RB, and CS. The resistors RA and RB are typically 500 W and are a lumped component made up of some serial resistance and the on resistance of the switches. The capacitor CS is typically 32 pF and is mainly the ADC sampling capacitor. This one-pole filter with a typical -3 dB cutoff frequency of 10 MHz reduces undesirable aliasing effects and limits the noise coming from the inputs. Because the input impedance of the AD7655 is very high, the AD7655 can be driven directly by a low impedance source without gain error. As shown in Figure 4, that allows an external one-pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the AD7655 analog input circuit. However, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades with the increase of the source impedance.
Driver Amplifier Choice
The AD7655 requires an external 2.5 V reference. The reference input should be applied to REF, REFA for Channel A, and to REFB for Channel B. The voltage reference input REF of the AD7655 has a dynamic input impedance; it should therefore be driven by a low impedance source with an efficient decoupling. This decoupling depends on the choice of the voltage reference but usually consists of a 1 mF ceramic capacitor and a low ESR tantalum capacitor connected to the REFA, REFB, and REFGND inputs with minimum parasitic inductance. 47 mF is an appropriate value for the tantalum capacitor when using one of the recommended reference voltages: The low noise, low temperature drift AD780 voltage reference The low cost AD1582 voltage reference
For applications using multiple AD7655s, it is more effective to buffer the reference voltage using the internal buffer. Each ADC should be decoupled individually. Care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter is applicable. For instance, a 15 ppm/C tempco of the reference changes the full scale by 1 LSB/C.
Power Supply
Although the AD7655 is easy to drive, the driver amplifier needs to meet at least the following requirements: The driver amplifier and the AD7655 analog input circuit have to be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier's data sheet, the settling at 0.1% or 0.01% is more commonly specified.
The AD7655 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 5. The AD7655 is independent of power supply sequencing, once OVDD does not exceed DVDD by more than 0.3 V, and thus is free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 6.
REV. 0
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AD7655
70
t2 t1
65
CNVST
60 PSRR - dB
t 14
A0
t 15
55
BUSY
50
t3 t4
45
EOC
t 10 t5
t 11 t 12
CONVERT A
t 13 t6
CONVERT B ACQUIRE CONVERT
40
1
10
100 FREQUENCY - kHz
1000
10000
MODE ACQUIRE
Figure 6. PSRR vs. Frequency
POWER DISSIPATION
t7
t8
Figure 8. Conversion Control
In impulse mode, the AD7655 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low, which allows significant power savings when the conversion rate is reduced, as shown in Figure 7. This feature makes the AD7655 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND) and OVDD should not exceed DVDD by more than 0.3 V.
1000
In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7655 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7655 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7655 could sometimes run slightly faster than the guaranteed limits in the impulse mode of 888 kSPS. This feature does not exist in normal mode. Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels, and with minimum overshoot and undershoot or ringing. For applications where the SNR is critical, the CNVST signal should have a very low jitter. Some solutions to achieve this are to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high frequency low jitter clock, as shown in Figure 4.
t9
RESET
POWER DISSIPATION - mW
NORMAL 100
10
IMPULSE
1 BUSY
0.1
1
100 10 SAMPLING RATE - kSPS
1000 DATA BUS
Figure 7. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
CNVST
t8
Figure 8 shows the detailed timing diagrams of the conversion process. The AD7655 is controlled by the signal CNVST, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of the CS and RD signals. The A0 signal is the MUX select signal that chooses which input signal is to be sampled. When high, INx1 is chosen and when low, INx2 is chosen, where x is either A or B. It should be noted that this signal should not be changed during the acquisition phase of the converter.
Figure 9. Reset Timing
DIGITAL INTERFACE
The AD7655 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7655 digital interface also accommodates either 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7655 to the host system interface digital supply.
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AD7655
Signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7655 in multicircuit applications and is held low in a single AD7655 design. RD is generally used to enable the conversion result on the data bus. In parallel mode, signal A/B allows the choice of reading either the output of Channel A or Channel B, whereas in serial mode, signal A/B controls which channel is output first.
CS = RD = 0
PARALLEL INTERFACE
The AD7655 is configured to use the parallel interface (Figure 10) when SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase or during the other channel's conversion, or during the following conversion as shown, respectively, in Figures 11 and 12. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 13, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is low. When BYTESWAP is high, the LSB and MSB bytes are swapped, the LSB is output on D[15:8], and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0].
t1
CNVST
t 16
BUSY
t4 t3
EOC t 10
t 17
DATA BUS
PREVIOUS CHANNEL A OR B
PREVIOUS CHANNEL B OR NEW A
NEW A OR B
CS
Figure 10. Master Parallel Data Timing for Reading (Continuous Read)
CS
RD
BYTE
PINS D[15:8]
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
RD
PINS D[7:0] HI-Z
t18
LOW BYTE
t18
HIGH BYTE
t19
HI-Z
BUSY
Figure 13. 8-Bit Parallel Interface
DATA BUS CURRENT CONVERSION
t18
t19
CS
Figure 11. Slave Parallel Data Timing for Reading (Read after Convert)
CS = 0 CNVST, RD
RD
A/B
t1
DATA BUS HI-Z CHANNEL A CHANNEL B HI-Z
t 10
EOC BUSY
t 12 t 11 t 13
t18 t20
Figure 14. A/B Channel Reading
t4 t3
DATA BUS
PREVIOUS CONVERSION
The detailed functionality of A/B is explained in Figure 14. When high, the data from Channel A is available on the data bus. When low, the data bus now carries output from Channel B. Note that Channel A can be read immediately after conversion is done (EOC), while Channel B is still in its converting phase.
SERIAL INTERFACE
t 18
t 19
Figure 12. Slave Parallel Data Timing for Reading (Read during Convert)
The AD7655 is configured to use the serial interface when SER/PAR is held high. The AD7655 outputs 32 bits of data, MSB first, on the SDOUT pin. The order of the channels being output is controlled by A/B. When HIGH, Channel A is output first; when LOW, Channel B is output first. Unlike in parallel mode, Channel A data is updated only after Channel B conversion. This data is synchronized with the 32 clock pulses provided on the SCLK pin.
REV. 0
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AD7655
MASTER SERIAL INTERFACE Internal Clock
Figures 15 and 16 show the detailed timing diagrams of these two modes. Usually, because the AD7655 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. In read after conversion mode, it should be noted that unlike in other modes, the signal BUSY returns low after the 32 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. One advantage of this mode is
The AD7655 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7655 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. The output data is valid on both the rising and falling edge of the data clock. Depending on RDC/SDIN input, the data can be read after each conversion or during the following conversion.
CS, RD
EXT/INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
A/B = 1
t3
CNVST
BUSY EOC
t35 t12 t13 t36 t37 t32 t25 t26 t27 t28
1 2 16 17 30 31
SYNC
t21
t31 t33
32
SCLK
t22 t34
SDOUT X CH A D15 CH A D14 CH B D2 CH B D1 CH B D0
t23
t29
t30
Figure 15. Master Serial Data Timing for Reading (Read after Convert)
CS, RD
EXT/INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
A/B = 1
t1
CNVST
t3
BUSY
t 12
EOC
t 10 t 24
t 11
t 13 t 32
SYNC
t 21
t 26 t 27 t 28
1 2 16 1 2
t 31 t 33
16
SCLK
t 22 t 25
t 34
SDOUT X CH A D15 CH A D14 CH A D0 CH B D15 CH B D14 CH B D0
t 23
t 29
t 30
Figure 16. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
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AD7655
that it can accommodate slow digital hosts because the serial clock can be slowed down by using DIVSCLK. In read during conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. The SYNC signal goes low after the LSB of each channel has been output.
SLAVE SERIAL INTERFACE External Clock
The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figures 17 and 18 show the detailed timing diagrams of these methods. While the AD7655 is performing a bit decision, it is important that voltage transients do not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase of each channel because the AD7655 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of EOC high.
RD = 0 A/B = 1
The AD7655 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS and the data are output when both CS and RD are low. Thus, depending on CS, the data can be read after each conversion or during the following conversion.
EXT/INT = 1 CS
INVSCLK = 0
EOC
BUSY
t 42 t 43 t 44
SCLK 1 2 3 30 31 32 33 34
t 38
SDOUT X CH A D15
t 39
CH A D14 CH A D13 CH B D1 CH B D0 X CH A D15 X CH A D14
t 23
t 41
X CH A D15 X CH A D14 X CH A D13 X CH B D1 X CH B D0 Y CH A D15 Y CH A D14
SDIN
t 40
Figure 17. Slave Serial Data Timing for Reading (Read after Convert)
EXT/INT = 1 CS INVSCLK = 0 RD = 0 A/B = 1
t 10
CNVST
t 12 t 11
EOC
t 13
BUSY
t3
t 42 t 43 t 44
1 2 3 31 32
SCLK
t 38
SDOUT X
t 39
CH A D15 CH A D14 CH A D13 CH B D1 CH B D0
t 23
Figure 18. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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AD7655
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes. Figure 18 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the results of this conversion can be read while both CS and RD are low. The data from both channels are shifted out, MSB first, with 32 clock pulses and are valid on both the rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is to be able to read the data at any speed up to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7655 provides a daisy-chain feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when it is desired, as it is for instance in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 19. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Therefore, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle.
External Clock Data Read during Conversion
prevent incomplete data reading. There is no daisy-chain feature in this mode, and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated.
BUSY OUT BUSY BUSY
AD7655
#2 (UPSTREAM)
AD7655
#1 (DOWNSTREAM)
RDC/SDIN
SDOUT CNVST CS SCLK
RDC/SDIN
SDOUT CNVST CS SCLK
DATA OUT
SCLK IN CS IN CNVST IN
Figure 19. Two AD7655s in a Daisy-Chain Configuration
MICROPROCESSOR INTERFACING
Figure 18 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 32 clock pulses, and is valid on both rising and falling edges of the clock. The 32 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to
The AD7655 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7655 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7655 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the AD7655 with an SPI equipped DSP, the ADSP-219x.
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AD7655
SPI Interface (ADSP-219x)
Figure 20 shows an interface diagram between the AD7655 and an SPI equipped DSP, ADSP-219x. To accommodate the slower speed of the DSP, the AD7655 acts as a slave device and data must be read after conversion. This mode also allows the daisy chain feature. The convert command could be initiated in response to an internal timer interrupt. The 32-bit output data are read with two SPI 16-bit wide access. The reading process could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The serial peripheral interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock phase bit (CPHA) = 1 by writing to the SPI control register (SPICLTx).
DVDD
AD7655*
SER/PAR EXT/INT BUSY CS SDOUT RD INVSCLK SCLK CNVST
ADSP-219x*
coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7655 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply's impedance presented to the AD7655 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply's pins, AVDD, DVDD, and OVDD close to and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 mF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7655 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if there is no separate supply available to connect the DVDD digital supply to the analog supply AVDD through an RC filter, as shown in Figure 5, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7655 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances.
Evaluating the AD7655 Performance
PFx SPIxSEL (PFx) MISOx SCKx PFx or TFSx
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing the AD7655 to SPI Interface
APPLICATION HINTS Layout
The AD7655 has very good immunity to noise on the power supplies, as seen in Figure 5. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7655 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7655, or at least as close as possible to the AD7655. If the AD7655 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7655. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7655 to avoid noise
A recommended layout for the AD7655 is outlined in the documentation of the evaluation board for the AD7655. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval-Control BRD2.
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AD7655
OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48)
Dimensions shown in millimeters
1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 9.00 BSC
48 1 37 36
1.45 1.40 1.35
0.20 0.09
SEATING PLANE
TOP VIEW
(PINS DOWN)
7.00 BSC
0.15 0.05
SEATING PLANE
7 3.5 0 0.08 MAX COPLANARITY
VIEW A
12 13 24 25
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BBC
48-Lead Lead Frame Chip Scale Package [LFCSP] (CP-48)
Dimensions shown in millimeters
0.30 0.23 0.18
48 1
7.00 BSC SQ
0.60 MAX 0.60 MAX
37 36
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
BOTTOM VIEW
5.25 5.10 SQ 4.95
0.50 0.40 0.30 1.00 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08
25 24
12 13
1.00 0.90 0.80 0.20 REF
5.50 REF
12 MAX
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
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PRINTED IN U.S.A.
C03536-0-2/03(0)

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